module mod_b (
    input clk,
    input rst_n,

    output reg emit_sig,
    input back_req,
    output reg backgot
);

///
/// 检测 上升沿
///
wire backreq_posedge;
reg  backreq_d0;
reg  backreq_d1;

assign backreq_posedge = ~backreq_d0 & (backreq_d1);

// 两拍检测法-检测
always @ (posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        backreq_d0 <= 0;
        backreq_d1 <= 0;
    end else begin
        backreq_d0 <= back_req;
        backreq_d1 <= backreq_d0;
    end
end


reg[31:0] _cnt;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        _cnt <= 32'd0;
        emit_sig <= 1'b0;
    end else begin
        _cnt <= _cnt + 32'd1;
        // if (_cnt == 32'd5)   //不是每次都能被同步到
        if ((_cnt == 32'd5) || (_cnt == 32'd6))  // 仿真测试证明，emit_sig用2个周期，脉冲宽度则高于mod_a的时钟宽度，上升沿检测就才每次都奏效。
        // if ((_cnt >= 32'd5) && (_cnt <= 32'd16)) // 脉冲高电平宽度对于 上升沿检测没有影响
            emit_sig <= 1'b1;
        else if (_cnt < 32'd20) begin
            emit_sig <= 1'b0;
        end else begin
            _cnt <= 32'd0;
            emit_sig <= 1'b0;
        end
    end
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        backgot <= 1'b0;
    end else begin
        if (backreq_posedge)
            backgot <= 1'b1;
        else
            backgot <= 1'b0;
    end
end

endmodule 
